Semiconductor device and semiconductor device manufacturing method

ABSTRACT

A semiconductor device having a low on resistance and high integration level with respect to the surface area of a substrate is provided. In the semiconductor device, a first trench, a second trench, and a third trench are provided in an element formation region provided on a semiconductor substrate. Metal is deposited within the first trench and second trench, to form a drain electrode and a source electrode, respectively. Polysilicon is deposited inside the third trench with a gate insulating film intervening, and a gate electrode is formed.

CROSS-REFERENCE TO RELATED APPLICATION

This Application is based on, and claims priority to, Japanese PatentApplication No. 2007-251410 filed on Sep. 27, 2007, the contents ofwhich are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a semiconductor device and to a manufacturingmethod of a semiconductor device, and in particular relates to a MOSFETwith a three-dimensional structure in which a MOS structure portion isformed in a direction perpendicular to a semiconductor substrate.

2. Description of the Related Art

In the prior art, horizontal-type MOSFETs (Metal Oxide SemiconductorField Effect Transistors), formed in a planar manner on a substrate, andTFTs (Thin Film Transistors), in which silicon is evaporation-depositedon a substrate, are well-known. MOSFETs and TFTs have evolved,accompanying demands for device miniaturization, with smaller elementpitches through reduced gate lengths (hereafter “L lengths”), as well asthe ability to pass larger currents by increasing gate widths (hereafter“W lengths”). Here the gate length is the length of the gate electrodein the direction in which carriers move between source and drain, andthe gate width is the length of the gate electrode in the directionperpendicular to the gate length.

However, because of the need to secure a breakdown voltage for theelement, there are limits to the extent to which the L length can bereduced. And, in a planar-structure device there is a limit to theextent to which the W length can be increased. On the other hand, amongdiscrete type MOSFETs, vertical type MOSFETs are known in which thedrain and source are formed above and below the substrate, and currentflows perpendicularly to the substrate.

Further, a trench lateral power MOSFET (TPLM) is known, in which a gateelectrode is formed on a trench side wall, and current flows from theupper face of the substrate toward the trench bottom face (for example,see Japanese Patent Laid-open No. 2006-216863). FIG. 16 is anexplanatory diagram showing the cross-sectional structure of a trenchlateral power MOSFET. As shown in FIG. 16, the trench lateral powerMOSFET 1600 is provided with an n-type well region 1602 in the surfaceregion of a p-type semiconductor substrate 1601. A trench 1605 is formedfrom the substrate surface in the well region 1602. And, an n-typeextended drain region 1603 to serve as a drift region is formed so as tosurround the bottom portion of the trench 1605.

A high-concentration n-type drain region 1606 is provided in thesubstrate surface layer on the side of the trench 1605. Between then-type drain region 1606 and the extended drain region 1603 is providedan n-type offset region 1608. And, on the opposite side of the trench1605 from the n-type drain region 1606 is provided a p-type offsetregion 1604 to serve as the channel region, in contact with the extendeddrain region 1603. In the substrate surface layer of the offset region1604 is provided a high-concentration n-type source region 1607, incontact with the trench 1605.

Further, in the trench 1605, on the side wall on the side in contactwith the offset region 1604, are provided a gate oxide film 1613 tobecome the gate insulating film and a gate polysilicon electrode 1611 toserve as the gate electrode. In the trench 1605, on the side wall on theside in contact with the n-type drain region 1606, are provided a fieldplate oxide film 1614 to serve as a field plate insulating film and afield plate 1612. And, an interlayer insulating film 1615 fills betweenthe gate polysilicon electrode 1611 and the field plate 1612.

In a trench-type MOSFET, the structure in the length direction of anordinary MOSFET is formed perpendicularly to the substrate. Consequentlyin a trench-type MOSFET the element pitch can be made small comparedwith an ordinary MOSFET, so that the W length of the entire element canbe increased. Also, because the current flowing in the element isproportional to the W length, in a trench lateral MOSFET the onresistance can be made smaller.

If it were possible to form an element with a structure in which the Wlength was extended in the substrate interior direction, then the Wlength of the overall element could be made markedly longer, and adevice with a low on resistance could be formed. Based on this concept,MOSFETs with three-dimensional structures, such as Fin-gate MOSFETs andsimilar devices, have been developed (see for example Japanese PatentLaid-open No. 51-147269, Japanese Patent Laid-open No.2005-(corresponding to U.S. Pat. No. 6,921,942 B2), and Japanese PatentLaid-open No. 2002-26311 (corresponding to U.S. Pat. No. 6,469,349 B2and one other)).

For example, in the case of a 20 V-class device, the pitch of a planarDMOSFET is 4 μm, and the pitch of a trench lateral power MOSFET is 2.5μm. On the other hand, in the case of MOSFETs with a three-dimensionalstructure, if the two dimensions along the substrate surface are the Xdirection and the Y direction, and the substrate internal direction isthe Z direction, then the pitch in the X direction is the same 4 μm asfor a planar device, and the pitch in the Y direction is 1.5 μm. TheY-direction pitch is smaller than the pitch for a trench lateral powerMOSFET because there is no need to perform ion implantation to form thesource region and drain region. In this case, if the drain-gate depth(Z-direction dimension) is 1.5 μm, then the W length is the same as fora planar device. And, if the trench gate depth is 2.4 μm, then the Wlength is the same as for a trench lateral power MOSFET. Hence if thetrench gate depth is 5 μm, then a W length twice that of a trenchlateral power MOSFET can be secured.

However, a Fin gate MOSFET requires that accurate patterning beperformed within the trench, and there is the problem that as the trenchaspect ratio rises, fine device formation becomes impossible. Further,in order to increase the device W length, a deep trench must be formed;but in order to keep the aspect ratio from becoming high, the trenchwidth must also be made broad. As a result, there is the problem that ina Fin gate MOSFET the density of the MOS structure which can be formedon trench side walls is decreased, and the area efficiency is worsened.

SUMMARY OF THE INVENTION

In order to resolve the above-described problems of the prior art, thisinvention has as an object the provision of a semiconductor device witha low on resistance and high integration level with respect to thesubstrate surface area. Also, this invention has as an object theprovision of a method for manufacturing semiconductor devices with a lowon resistance and high integration level with respect to the substratesurface area, without accompanying complex processes.

In order to resolve the above-described problems and attain theseobjects, in one aspect of a semiconductor device according to theinvention, a first trench is provided in a semiconductor region of afirst conduction type, and a drain electrode, formed from metal, isprovided within the first trench. On the periphery of the first trenchis formed a drain region of a second conduction type, and on theperiphery of the drain region is formed a drift region of the secondconduction type, with an impurity concentration lower than that of thedrain region. In the first-conduction-type semiconductor region, isprovided a second trench so as to be parallel to the first trench;within the second trench is provided a source electrode, formed frommetal; and on the periphery of the second trench is formed a sourceregion of the second conduction type. Also, in the first-conduction-typesemiconductor region is provided a third trench, perpendicular to thefirst trench and second trench. The third trench is in contact with thedrift region and with the source region. Within the third trench isprovided a gate electrode, formed from polysilicon with an insulatingfilm intervening. On the surface of the first-conduction-typesemiconductor region is provided a pickup region of the first conductiontype, removed from the drift region and source region. A plurality ofgate electrodes and pickup regions may be provided, alternately.

Further, in a semiconductor device manufacturing method formanufacturing the semiconductor device according to the above-mentionedaspect of the invention, first, a first trench and a second trench areformed with substantially the same width and in parallel in asemiconductor region of a first conduction type, and a third trench ofwidth narrower than that of the first trench and second trench, isformed perpendicularly to the first trench and second trench. Next, aninsulating film is formed on a side wall of the first trench, on a sidewall of the second trench, and on a side wall of the third trench. Then,polysilicon is deposited so as to cover the insulating film formed onthe side wall of the first trench and the side wall of the secondtrench, and so as to fill the interior of the third trench. Then, theinsulating film and the polysilicon on the side wall of the first trenchand on the side wall of the second trench are removed, the insulatingfilm and the polysilicon on the periphery of an aperture portion of thethird trench are removed, and a gate insulating film and a gateelectrode are formed within the third trench. Then metal is depositedwithin the first trench and the second trench, and a drain electrode isformed within the first trench and a source electrode is formed withinthe second trench.

Further, in another semiconductor device manufacturing method formanufacturing a semiconductor device according to the above-mentionedaspect of the invention, first, a first trench and a second trench areformed with substantially the same width and in parallel in asemiconductor region of a first conduction type, and a third trench ofwidth narrower than that of the first trench and second trench, isformed perpendicularly to the first trench and second trench. Next, adrift region is formed, in contact with the third trench, along theperiphery of the side wall of the first trench within thefirst-conduction-type semiconductor region. Then, after forming aninsulating film on the side wall of the first trench, the side wall ofthe second trench, and the side wall of the third trench, polysilicon isdeposited so as to cover the insulating film formed on the side wall ofthe first trench and the side wall of the second trench, and so as tofill the interior of the third trench. Then, the insulating film and thepolysilicon on the side wall of the first trench and side wall of thesecond trench are removed, and the insulating film and the polysiliconon the periphery of an aperture portion of the third trench are removed,and in addition a gate insulating film and a gate electrode are formedwithin the third trench. Next, a drain region of a second conductiontype is formed along the periphery of the first trench within thefirst-conduction-type semiconductor region, and a source region of thesecond conduction type is formed along the periphery of the side wall ofthe second trench. Then, a pickup region of the first conduction type isformed, removed from the drift region and source region, in a region ofthe surface of the first-conduction-type semiconductor region in whichthe third trench is not formed. Finally, metal is deposited within thefirst trench and second trench, and a drain electrode is formed withinthe first trench and a source electrode is formed within the secondtrench.

In the process of formation of the drift region in the above-describedother manufacturing method, the region other than the aperture portionof the first trench may be masked, impurities of the second conductiontype may be implanted from the perpendicular direction and obliquedirections into the aperture portion of the first trench, and heattreatment may be performed to form the drift region. Also, in theprocess of formation of the drain region and source region, the regionother than the aperture portions of the first trench and second trenchmay be masked, impurities of the second conduction type may be implantedfrom the perpendicular direction and oblique directions into theaperture portions of the first trench and second trench, and heattreatment may be performed to form the drain region and source region.

In another aspect of a semiconductor device according to the invention,the semiconductor device comprises a first trench, provided in asemiconductor region of a first conduction type, a drain electrode,formed within the first trench, a second trench, provided in thesemiconductor region of the first conduction type, and a sourceelectrode, formed within the second trench. The semiconductor devicefurther comprises a third trench narrower than the first trench andsecond trench, provided in the semiconductor region of the firstconduction type, and in contact with a drift region associated with thefirst trench and a source region associated with the second trench and agate electrode, formed within the third trench.

The semiconductor device according to the above-described other aspectmay further comprise a drain region of a second conduction type, formedon a periphery of the first trench. The drift region may be of thesecond conduction type, be formed on the periphery of the drain region,and have an impurity concentration lower than that of the drain region.The second trench may be parallel with the first trench, and the thirdtrench may be perpendicular to the first trench and the second trench.In the semiconductor device, the source region may be of the secondconduction type, and formed on a periphery of the second trench. Thesemiconductor device may further comprise a pickup region of the firstconduction type, provided on a surface of the semiconductor region ofthe first conduction type, and removed from the drift region and thesource region. The gate electrode may be formed of polysilicon, and thedrain electrode and the source electrode may be formed from metal. Aplurality of the gate electrodes and a plurality of the pickup regionsmay be provided alternately.

By means of a semiconductor device of this invention, there is theadvantageous result that a semiconductor device can be obtained having alow on resistance and high integration level with respect to thesubstrate surface area. Further, by means of a semiconductor devicemanufacturing method of this invention, a semiconductor device having alow on resistance and high integration level with respect to thesubstrate surface area can be manufactured, without accompanying complexprocesses.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view showing the structure of the semiconductor deviceaccording to the invention;

FIG. 2 is a cross-sectional view along the direction of the line segmentA-A′ in FIG. 1;

FIG. 3 is a cross-sectional view along the direction of the line segmentB-B′ in FIG. 1;

FIG. 4 is an explanatory diagram showing a stage of a semiconductordevice manufacturing process for manufacturing the semiconductor deviceaccording to the invention as shown in FIGS. 1-3;

FIG. 5 is an explanatory diagram showing another stage of thesemiconductor device manufacturing process;

FIG. 6 is an explanatory diagram showing a still further stage of thesemiconductor device manufacturing process;

FIG. 7 is an explanatory diagram showing a still further stage of thesemiconductor device manufacturing process;

FIG. 8 is an explanatory diagram showing a still further stage of thesemiconductor device manufacturing process;

FIG. 9 is an explanatory diagram showing a still further stage of thesemiconductor device manufacturing process;

FIG. 10 is an explanatory diagram showing a still further stage of thesemiconductor device manufacturing process;

FIG. 11 is an explanatory diagram showing a still further stage of thesemiconductor device manufacturing process;

FIG. 12 is an explanatory diagram showing a still further stage of thesemiconductor device manufacturing process;

FIG. 13 is an explanatory diagram showing a still further stage of thesemiconductor device manufacturing process;

FIG. 14 is an explanatory diagram showing a still further stage of thesemiconductor device manufacturing process;

FIG. 15 is an explanatory diagram showing a still further stage of thesemiconductor device manufacturing process; and

FIG. 16 is an explanatory diagram showing the cross-sectional structureof a conventional trench lateral power MOSFET.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Below, structures of a semiconductor device and operations of asemiconductor device manufacturing method according to the invention areexplained in detail, referring to the attached drawings.

FIG. 1 is a plan view showing the structure of the semiconductor deviceaccording to the invention. FIG. 2 is a cross-sectional view in thedirection along line segment A-A′ in FIG. 1, and FIG. 3 is across-sectional view in the direction along line segment B-B′ in FIG. 1.The semiconductor device 100 is an n-channel MOSFET with athree-dimensional structure. FIG. 4 is a cross-sectional view of thesubstrate on which the semiconductor device of the aspect is formed. InFIG. 1 to FIG. 3, an interlayer insulating film and metal wiring formedon the surface of the semiconductor device 100 are omitted.

As shown in FIG. 1 to FIG. 3, in the semiconductor device 100, a drainelectrode 102 is formed within the trench 112 formed in the Y directionof the surface of the element formation region 101 (see FIG. 4) on asemiconductor substrate, and a source electrode 103 is formed within thetrench 113 formed in the same Y direction. On the periphery of the drainelectrode 102 is formed an n⁺ drain region 106. Also, an n⁻ drift region107 is formed on the periphery of the n⁺ drain region 106, and an n⁺source region 108 is formed on the periphery of the source electrode103.

Also, a gate electrode 104 is formed, with a gate insulating film 105intervening, within the trench 114 formed in the x direction of thesurface of the element formation region 101. The trench 114 is incontact with the n⁻ drift region 107 and n⁺ source region 108. Also, ap⁺ pickup region 109 is formed parallel to the trench 114 on the surfaceof the element formation region 101.

The pitch Px in the X direction of the semiconductor device 100 (thedistance between the X direction center of the drain electrode 102 andthe X direction center of the n⁺ source electrode 103) is for example4.5 μm. Also, the pitch Py in the Y direction of the semiconductordevice 100 (the distance between Y direction centers of adjacent gateelectrodes 104) is for example 1.5 μm.

More specifically, the width in the X direction of the trench 112 forthe drain electrode 102 and of the trench 113 for the source electrode103 is for example 1 μm. And, the width in the X direction of the trench114 for the gate electrode 104 is for example 1.5 μm. The width in the Ydirection of the trench 114 for the gate electrode 104 is for example0.4 μm. And, the distance in the X direction between the trench 112 forthe drain electrode 102 and the trench 114 for the gate electrode 104 is1 μm. The distance in the X direction between the trench 113 for thesource electrode 103 and the trench 114 for the gate electrode 104 is 1μm.

As shown in FIG. 4, the semiconductor substrate on which thesemiconductor device 100 is formed is prepared by forming, on thesurface of a p-type semiconductor substrate 201, a first p epitaxiallayer 203 with a p layer 202 intervening, and a second p epitaxial layer205 with an n layer 204 intervening. An epitaxial layer is anepitaxially grown layer. The first p epitaxial layer 203 and second pepitaxial layer 205 are separated by an n-type separation region 206.The first p epitaxial layer 203 is a low-side p-type semiconductorregion, and the second p epitaxial layer 205 is a high-side p-typesemiconductor region. Hereafter, the first p epitaxial layer 203 andsecond p epitaxial layer 205 are together called the element formationregion 101.

Next, processes in the manufacture of the semiconductor device 100 areexplained. FIG. 4 to FIG. 15 are explanatory diagrams showing stages ofthe manufacturing processes. In FIG. 5 to FIG. 15, cross-sectional viewsalong the line segment A-A′ in FIG. 1 are called “A-A′ cross-sectionalviews” and cross-sectional views along line segment B-B′ in FIG. 1 arecalled “B-B′ cross-sectional views”.

First, as shown in FIG. 4, p-type impurities and n-type impurities areimplanted from the surface of a p-type semiconductor substrate 201, toform a p layer 202 and an n layer 204. Next, epitaxial growth is used toform a first p epitaxial layer 203 and second p epitaxial layer 205 onthe surfaces of the p layer 202 and n layer 204 respectively. Then, ann-type diffusion layer is used to form a separation region 206, enablingformation of a semiconductor substrate with the structure shown in FIG.4.

The p layer 202 and n layer 204 may also be formed by first forming thefirst p epitaxial layer 203 and second p epitaxial layer 205 on thesurface of the semiconductor substrate 201, and then implantingimpurities from the surface of the first p epitaxial layer 203 andsecond p epitaxial layer 205. Also, the separation region 206 may alsobe formed by means of a trench or a diffusion layer formed within atrench.

Next, as shown in the A-A′ cross-sectional view of FIG. 5, after forminga silicon oxide film 301 over the entire surface of the elementformation region 101, patterning is performed to open regions in whichto form the trenches 112 to 114. Then, using the silicon oxide film 301as a mask, etching is performed to form the trenches 112 to 114. Thedepth of the trenches 112 to 114 (Z-direction distance) is for example 3μm.

Next, as shown in the A-A′ cross-sectional view of FIG. 6, afterapplying resist 302 to the surface of the element formation region 101and within the trenches 112 to 114, patterning is performed to removeresist 302 within the trench 112 for the drain electrode 102 and fromthe vicinity of the aperture portion of the trench 112. Then, using theresist 302 as a mask, n-type impurities are implanted, in theperpendicular direction and in oblique directions, within the trench112. Then heat treatment is performed to form an n⁻ drift region 107. Atthis time, the n⁻ drift region 107 reaches an end portion of the trench114 for the gate electrode 104.

Next, as shown in the A-A′ cross-sectional view of FIG. 7, afterremoving silicon oxide film 301 and resist 302, a silicon oxide film 303is formed on the surface of the element formation region 101 and thesurfaces within the trenches 112 to 114. Then, polysilicon 304 isdeposited onto the surface of the silicon oxide film 303. At this time,the interior of the trench 114 for the gate electrode 104 is completelyfilled with the polysilicon 304. On the other hand, the trench 112 forthe drain electrode 102 and trench 113 for the source electrode 103 arenot completely filled with the polysilicon 304, and spaces are left inthe interiors thereof. This is achieved by setting the film thickness ofthe polysilicon 304 and the widths of the trenches 112 to 114 toappropriate values.

Next, as shown in the A-A′ cross-sectional view of FIG. 8, isotropicetching is performed to remove polysilicon 304. At this time, thepolysilicon 304 deposited within the trench 112 for the drain electrode102 and within the trench 113 for the source electrode 103 is completelyremoved. On the other hand, a portion of the upper portion (on theperiphery of the aperture portion) of the polysilicon 304 deposited inthe trench 114 for the gate electrode 104 is removed, but most of thepolysilicon within the trench 114 is not removed. This is so that theinterior of the trench 114 is completely filled with polysilicon 304 sothat the surface area is reduced, and consequently the etching rate isslower compared with the polysilicon 304 in the trenches 112 and 113.Further, the polysilicon 304 remaining within the trench 114 becomes thegate electrode 104.

Next, as shown in the A-A′ cross-sectional view of FIG. 9, resist 305 isdeposited on the surface of the element formation region 101. Then,patterning is performed to remove resist 305 within the trench 112 forthe drain electrode 102 and on the periphery of the aperture portionthereof, and within the trench 113 for the source electrode 103 and onthe periphery of the aperture portion thereof.

Next, as shown in the A-A′ cross-sectional view of FIG. 10, using theresist 305 as a mask, polysilicon oxide film 303 is removed from theinteriors of the trenches 112 and 113 and from the periphery of theaperture portions thereof. Silicon oxide film 303 remaining within thetrench 114 for the gate electrode 104 and on the periphery of theaperture portion thereof becomes the gate insulating film 105. And,using the resist 305 as a mask, n-type impurities are implanted into thetrenches 112 and 113 from the perpendicular direction and from obliquedirections. And, heat treatment is performed to form an n⁺ drain region106 and an n⁺ source region 108. Then the resist 305 is removed.

Next, as shown in the B-B′ cross-sectional view of FIG. 11, resist 306is again deposited on the surface of the element formation region 101and within the trenches 112 to 114. Patterning is performed to removethe resist 306 in the region in which a p⁺ pickup region 109 is to beformed, and silicon oxide film 303 is further removed. Then, p-typeimpurities are implanted, and heat treatment is performed to form the p⁺pickup region 109. Then the resist 306 is removed.

Next, as shown in the A-A′ cross-sectional view of FIG. 12 and the B-B′cross-sectional view of FIG. 13, silicon oxide film 307, to serve as aninterlayer insulating film, is formed on the surface of the elementformation region 101 and within the trenches 112 to 114. Resist 308 isdeposited on the surface of the silicon oxide film 307, and patterningis performed to remove resist 308 from within the trenches 112 and 113and the peripheries of the aperture portions thereof and from thesurface of the p⁺ pickup region 109.

Then, as shown in the A-A′ cross-sectional view of FIG. 14 and the B-B′cross-sectional view of FIG. 15, the resist 308 is used as a mask toperform patterning, to remove silicon oxide film 307 from within thetrenches 112 and 113 and the peripheries of the aperture portionsthereof, and from the surface of the p⁺ pickup region 109. Then, theresist 308 is removed, and the interiors of the trenches 112 and 113 andthe peripheries of the aperture portions thereof are filled withtungsten or another metal, to form the drain electrode 102 and sourceelectrode 103. Also, the surface of the p⁺ pickup region 109 is alsofilled with tungsten or another metal to form a contact region 309.Then, aluminum is deposited over the entire surface, and patterning isperformed to form aluminum wiring 310. By means of the above processes,a semiconductor device according to the invention can be manufactured.

As explained above, in a semiconductor device of this invention, byforming the MOS structure portion within the semiconductor substrate,the integration level with respect to the substrate surface area can beraised. Further, the device W length can be increased, so that the onresistance of the semiconductor device can be lowered.

Also, in a semiconductor device manufacturing method of this invention,by forming the trench for the gate electrode to be narrow compared withthe trench for the drain electrode and the trench for the sourceelectrode, polysilicon can be made to remain only in the trench for thegate electrode. By this means, the gate electrode can be formed ofpolysilicon, and the drain electrode and source electrode can be formedof metal.

Also, in a semiconductor device manufacturing method of this invention,by implanting impurities into the trench for the drain electrode andinto the trench for the source electrode from the perpendiculardirection and from oblique directions, a drain region and source regionare formed in trench side walls. By this means, the high-concentrationimpurity regions which serve as the drain region and the source regioncan be formed uniformly, in self-aligned fashion, to below thepolysilicon which serves as the gate electrode.

As explained above, a semiconductor device and a semiconductor devicemanufacturing method of this invention are effective for obtainingsemiconductor devices with a low on resistance and high integrationlevel with respect to the substrate surface area, and in particular areappropriate for MOSFETs with a three-dimensional structure, in which theMOS structure portion is formed in the direction perpendicular to thesemiconductor substrate.

Several embodiments of the present invention are specificallyillustrated and described herein. However, it will be appreciated thatmodifications and variations of the present invention are covered by theabove teachings and within the purview of the appended claims withoutdeparting from the spirit and intended scope of the invention.

1. A semiconductor device, comprising: a first trench, provided in asemiconductor region of a first conduction type; a drain electrode,formed from metal within the first trench; a drain region of a secondconduction type, formed on the periphery of the first trench; a driftregion of the second conduction type, formed on the periphery of thedrain region and having an impurity concentration lower than that of thedrain region; a second trench, provided in the semiconductor region ofthe first conduction type so as to be parallel to the first trench; asource electrode, formed from metal within the second trench; a sourceregion of the second conduction type, formed on the periphery of thesecond trench; a third trench, provided in the semiconductor region ofthe first conduction type perpendicularly to the first trench and thesecond trench, and in contact with the drift region and the sourceregion; a gate electrode, formed of polysilicon within the third trench,with an insulating film intervening; and a pickup region of the firstconduction type, provided on the surface of the semiconductor region ofthe first conduction type, and removed from the drift region and thesource region.
 2. The semiconductor device according to claim 1, whereina plurality of the gate electrodes and a plurality of the pickup regionsare provided alternately.
 3. The semiconductor device according to claim1, wherein the third trench is narrower than the first trench and thesecond trench.
 4. A semiconductor device manufacturing method,comprising the steps of: forming, in a semiconductor region of a firstconduction type, a first trench and a second trench in parallel and withsubstantially a same width, and forming a third trench perpendicularlyto the first trench and second trench, with a width narrower than thefirst trench and second trench; forming an insulating film on a sidewall of the first trench, a side wall of the second trench, and a sidewall of the third trench; depositing polysilicon so as to cover asurface of the insulating film formed on the side wall of the firsttrench and the side wall of the second trench, and so as to fill aninterior of the third trench; removing the insulating film and thepolysilicon from the side wall of the first trench and the side wall ofthe second trench, and removing the insulating film and the polysiliconfrom a periphery of an aperture portion of the third trench, to form agate insulating film and a gate electrode within the third trench; anddepositing metal within the first trench and the second trench, to forma drain electrode within the first trench and a source electrode withinthe second trench.
 5. The semiconductor device manufacturing methodaccording to claim 4, further comprising the steps of: forming, in thesemiconductor region of the first conduction type, a drift region alonga periphery of the side wall of the first trench, and in contact withthe third trench; forming a drain region of a second conduction type,within the semiconductor region of the first conduction type along theperiphery of the side wall of the first trench, and forming a sourceregion of the second conduction type along a periphery of the side wallof the second trench; and forming a pickup region of the firstconduction type, removed from the drift region and source region, in aregion of the surface of the semiconductor region of the firstconduction type in which the third trench is not formed.
 6. Thesemiconductor device manufacturing method according to claim 5, whereinin the step of forming the drift region, the region other than theaperture portion of the first trench is masked to implant impurities ofthe second conduction type into the aperture portion of the first trenchfrom a perpendicular direction and oblique directions, and heattreatment is performed to form the drift region.
 7. The semiconductordevice manufacturing method according to claim 5, wherein in the step offorming the drain region and the source region, the region other thanthe aperture portion of the first trench and the aperture portion of thesecond trench is masked to implant impurities of the second conductiontype into the aperture portion of the first trench and the apertureportion of the second trench from a perpendicular direction and obliquedirections, and heat treatment is performed to form the drain region andthe source region.
 8. The semiconductor device manufacturing methodaccording to claim 6, wherein in the step of forming the drain regionand the source region, the region other than the aperture portion of thefirst trench and the aperture portion of the second trench is masked toimplant impurities of the second conduction type into the apertureportion of the first trench and the aperture portion of the secondtrench from a perpendicular direction and oblique directions, and heattreatment is performed to form the drain region and the source region.9. A semiconductor device, comprising: a first trench, provided in asemiconductor region of a first conduction type; a drain electrode,formed within the first trench; a second trench, provided in thesemiconductor region of the first conduction type; a source electrode,formed within the second trench; a third trench narrower than the firsttrench and second trench, provided in the semiconductor region of thefirst conduction type, and in contact with a drift region associatedwith the first trench and a source region associated with the secondtrench; and a gate electrode, formed within the third trench.
 10. Thesemiconductor device according to claim 9, further comprising a drainregion of a second conduction type, formed on a periphery of the firsttrench.
 11. The semiconductor device according to claim 10, wherein thedrift region is of the second conduction type, is formed on theperiphery of the drain region, and has an impurity concentration lowerthan that of the drain region.
 12. The semiconductor device according toclaim 9, wherein the second trench is parallel with the first trench,and the third trench is perpendicular to the first trench and the secondtrench.
 13. The semiconductor device according to claim 9, wherein thesource region is of a second conduction type, and formed on a peripheryof the second trench.
 14. The semiconductor device according to claim 9,further comprising a pickup region of the first conduction type,provided on a surface of the semiconductor region of the firstconduction type, and removed from the drift region and the sourceregion.
 15. The semiconductor device according to claim 9, wherein thegate electrode is formed of polysilicon, and the drain electrode and thesource electrode are formed from metal.
 16. The semiconductor regionaccording to claim 14, wherein a plurality of the gate electrodes and aplurality of the pickup regions are provided alternately.